| No |
Authors |
Tile of the paper |
Journal / Conference Details |
Paper Link |
| 1 |
Bheemappa Halavar and Basavaraj Talawar |
Power and Performance Analysis of 3D Network-on-Chip Architectures |
Computers and Electrical Engineering Journal |
PDF |
| 2 |
Bheemappa Halavar, Ujjwal Pasupulety and Basavaraj Talawar |
Extending BookSim2.0 and HotSpot6.0 for power,performance and thermal evaluation of 3DNoC architectures |
Journal of Simulation Modelling Practice and Theory |
PDF |
| 3 |
Bheemappa Halavar and Basavaraj Talawar |
Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-Chip |
SPCOM 2018, Indian Institute of Science, Bangalore, India |
PDF |
| 4 |
Bheemappa Halavar and Basavaraj Talawar |
Accurate Performance Analysis of 3D Mesh Network on Chip Architectures |
IEEE CONECCT 2018, March., 16-17, IISc Bangalore, India. |
PDF |
| 5 |
Ujjwal Pasupulety, Bheemappa Halavar and Basavaraj Talawar |
Thermal Aware Design for Through- Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures |
8th Int'l Symp. on Embedded Computing & System Design (ISED 2018), 13-15, December, 2018, CUSAT, Kochi, India |
PDF |
| 6 |
Bheemappa Halavar and Basavaraj Talawar |
OP3DBFT: A Power and Performance Optimal 3D BFT NoC Architecture |
Intl. Conference on Intelligent Systems Design and Applications (ISDA 2018), 6-8 December, 2018, VIT, Vellore, India. |
PDF |
| 7 |
Ujjwal Pasupulety, Bheemappa Halavar and Basavaraj Talawar |
Accurate Power and Latency Analysis of a Through-Silicon Via (TSV) |
ICACCI'18, PES Institute of Technology, South Campus, Bangalore, India-2018 |
PDF |