NoCs on 3D ICs technology provides an opportunity to better the on chip communication delay, energy and area parameters compared to the 2D-NoCs. We are extending the existing simulators to support 3D-NoC topologies. Design space exploration of 3D-NoC is being driven by considering physical characteristics of vertical connections like Through Silicon Vias (TSVs). The exploration is aided using power, performance and cost metrics such as area, throughput, avg. flit latency, Energy per bit transferred, and EDP.